Verilog HDL : a guide to digital design and synthesis / Samir Palnitkar.Material type: TextLanguage: English Publication details: Upper Saddle River, NJ : SunSoft Press, 2003. Edition: 2nd edDescription: xlii, 450 p. : ill. ; 25 cmISBN: 0130449113; 9780130449115; 0132599708; 9780132599702Subject(s): Verilog (Computer hardware description language)DDC classification: 621.392 Online resources: WorldCat Details
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|621.392 CIA 2006 Advanced digital design with the verilog HDL /||621.392 CIA 2006 Advanced digital design with the verilog HDL /||621.392 PAD 2004 Design through Verilog HDL /||621.392 PAV 2003 Verilog HDL :||621.395 ATP PSPICE and MATLAB for electronics :||621.395 BAD 2004 Digital logic design principles /||621.395 BAD 2004 Digital logic design principles /|
"A Prentice Hall title."
"Professional technical reference"--Page  cover.
Includes Bibliographical References and Index
TOC (NOTE: Each chapter concludes with a Summary and Exercises.) About the Author. Foreword. Preface. Acknowledgments. I. BASIC VERILOG TOPICS. 1. Overview of Digital Design with Verilog HDL. Evolution of Computer-Aided Digital Design. Emergence of HDLs. Typical Design Flow. Importance of HDLs. Popularity of Verilog HDL. Trends in HDLs. 2. Hierarchical Modeling Concepts. Design Methodologies. 4-bit Ripple Carry Counter. Modules. Instances. Components of a Simulation. Example. 3. Basic Concepts. Lexical Conventions. Data Types. System Tasks and Compiler Directives. 4. Modules and Ports. Modules. Ports. Hierarchical Names. 5. Gate-Level Modeling. Gate Types. Gate Delays. 6. Dataflow Modeling. Continuous Assignments. Delays. Expressions, Operators, and Operands. Operator Types. Examples. 7. Behavioral Modeling. Structured Procedures. Procedural Assignments. Timing Controls. Conditional Statements. Multiway Branching. Loops. Sequential and Parallel Blocks. Generate Blocks. Examples. 8. Tasks and Functions. Difference between Tasks and Functions. Tasks. Functions. 9. Useful Modeling Techniques. Procedural Continuous Assignments. Overriding Parameters. Conditional Compilation and Execution. Time Scales. Useful System Tasks. II. ADVANCED VERILOG TOPICS. 10. Timing and Delays. Types of Delay Models. Path Delay Modeling. Timing Checks. Delay Back-Annotation. 11. Switch Level Modeling. Switching-Modeling Elements. Examples. 12. User-Defined Primitives. UDP basics. Combinational UDPs. Sequential UDPs. UDP Table Shorthand Symbols. Guidelines for UDP Design. 13. Programming Language Interface. Uses of PLI. Linking and Invocation of PLI Tasks. Internal Data Representation. PLI Library Routines. 14. Logic Synthesis with Verilog HDL. What Is Logic Synthesis? Impact of Logic Synthesis. Verilog HDL Synthesis. Synthesis Design Flow. Verification of the Gate-Level Netlist. Modeling Tips for Logic Synthesis. Example of Sequential Circuit Synthesis. 15. Advanced Verification Techniques. Traditional Verification Flow. Assertion Checking. Formal Verification. III. APPENDICES. Appendix A. Strength Modeling and Advanced Net Definitions. Strength Levels. Signal Contention. Advanced Net Types. Appendix B. List of PLI Routines. Conventions. Access Routines. Utility (tf_) Routines. Appendix C. List of Keywords, System Tasks and Compiler Directives. Keywords. System Tasks and Functions. Compiler Directives. Appendix D. Formal Syntax Definition. Source Text. Declarations. Primitive Instances. Module and Generated Instantiation. UDP Declaration and Instantiation. Behavioral Statements. Specify Section. Expressions. General. Appendix E. Verilog Tidbits. Appendix F. Verilog Examples. Synthesizable FIFO Model. Behavioral DRAW Model. Bibliography. Index.