Design through Verilog HDL / T.R. Padmanabhan, B. Bala Tripura Sundari.
By: Patmaṉāpaṉ, Ṭi. Ār
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Contributor(s): Tripura Sundari, B. Bala.
Material type: 
TextPublisher: Piscataway, NJ : Hoboken, NJ : Noida ; IEEE Press ; Wiley-Interscience, c2004Description: xii, 455 p. : ill. ; 25 cm.ISBN: 0471441481 (cloth).Subject(s): Verilog (Computer hardware description language)DDC classification: 621.392 Online resources: WorldCat details | E-book Fulltext | Item type | Current location | Collection | Call number | Copy number | Status | Date due | Barcode | Item holds |
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| 621.3916 MAP 2001 Personal computer hardware and troubleshooting / | 621.392 CIA 2006 Advanced digital design with the verilog HDL / | 621.392 CIA 2006 Advanced digital design with the verilog HDL / | 621.392 PAD 2004 Design through Verilog HDL / | 621.392 PAV 2003 Verilog HDL : | 621.395 ATP PSPICE and MATLAB for electronics : | 621.395 BAD 2004 Digital logic design principles / |
Includes bibliographical references (p. 449-450) and index.
Table of contents Machine generated contents note: 1. Introduction to VLSI Design --
2. Introduction to Verilog --
3. Language Constructs and Conventions in Verilog --
4. Gate Level Modeling --
1 --
5. Gate Level Modeling --
2 --
6. Modeling at Data Flow Level --
7. Behavioral Modeling --
1 --
8. Behavioral Modeling II --
9. Functions, Tasks, and User-Defined Primitives --
10. Switch Level Modeling --
11. System Tasks, Functions, and Compiler Directives --
12. Queues, Plas, and FSMS --
App. A Keywords and Their Significance --
App. B Truth Tables of Gates an Switches.
Electronic & Telecommunication Engineering
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