Design through Verilog HDL / T.R. Padmanabhan, B. Bala Tripura Sundari.
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EWU Library E-book | Non-fiction | 621.392 PAD 2004 (Browse shelf(Opens below)) | Not for loan | ||||
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EWU Library Reserve Section | Non-fiction | 621.392 PAD 2004 (Browse shelf(Opens below)) | C-1 | Not For Loan | 17507 | ||
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EWU Library Circulation Section | Non-fiction | 621.392 PAD 2004 (Browse shelf(Opens below)) | C-4 | Available | 20324 | ||
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EWU Library Circulation Section | Non-fiction | 621.392 PAD 2004 (Browse shelf(Opens below)) | C-5 | Available | 20325 |
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621.3916 MAP 2001 Personal computer hardware and troubleshooting / | 621.392 CIA 2006 Advanced digital design with the verilog HDL / | 621.392 CIA 2006 Advanced digital design with the verilog HDL / | 621.392 PAD 2004 Design through Verilog HDL / | 621.392 PAV 2003 Verilog HDL : | 621.395 ATP PSPICE and MATLAB for electronics : | 621.395 BAD 2004 Digital logic design principles / |
Includes bibliographical references (p. 449-450) and index.
TOC Machine generated contents note: 1. Introduction to VLSI Design --
2. Introduction to Verilog --
3. Language Constructs and Conventions in Verilog --
4. Gate Level Modeling --
1 --
5. Gate Level Modeling --
2 --
6. Modeling at Data Flow Level --
7. Behavioral Modeling --
1 --
8. Behavioral Modeling II --
9. Functions, Tasks, and User-Defined Primitives --
10. Switch Level Modeling --
11. System Tasks, Functions, and Compiler Directives --
12. Queues, Plas, and FSMS --
App. A Keywords and Their Significance --
App. B Truth Tables of Gates an Switches.
ETE
Tahur Ahmed
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