Design through Verilog HDL / T.R. Padmanabhan, B. Bala Tripura Sundari.

By: Patmaṉāpaṉ, Ṭi. Ār Contributor(s): Tripura Sundari, B. Bala Material type: Text

TextLanguage: English Publication details: Piscataway, NJ : Hoboken, NJ : Noida ; IEEE Press ; Wiley-Interscience, c2004. Description: xii, 455 p. : ill. ; 25 cmISBN: 0471441481 (cloth)Subject(s): Verilog (Computer hardware description language)DDC classification: 621.392 LOC classification: TK7885.7 | .P37 2004Online resources: WorldCat details | E-book Fulltext

Contents:

TOC Machine generated contents note: 1. Introduction to VLSI Design -- 2. Introduction to Verilog -- 3. Language Constructs and Conventions in Verilog -- 4. Gate Level Modeling -- 1 -- 5. Gate Level Modeling -- 2 -- 6. Modeling at Data Flow Level -- 7. Behavioral Modeling -- 1 -- 8. Behavioral Modeling II -- 9. Functions, Tasks, and User-Defined Primitives -- 10. Switch Level Modeling -- 11. System Tasks, Functions, and Compiler Directives -- 12. Queues, Plas, and FSMS -- App. A Keywords and Their Significance -- App. B Truth Tables of Gates an Switches.

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Holdings
Item type	Current library	Collection	Call number	Copy number	Status	Barcode
E-Book	Dr. S. R. Lasker Library, EWU E-book	Non-fiction	621.392 PAD 2004 (Browse shelf(Opens below))		Not for loan
Text	Dr. S. R. Lasker Library, EWU Reserve Section	Non-fiction	621.392 PAD 2004 (Browse shelf(Opens below))	C-1	Not For Loan	17507
Text	Dr. S. R. Lasker Library, EWU Circulation Section	Non-fiction	621.392 PAD 2004 (Browse shelf(Opens below))	C-2	Available	17508
Text	Dr. S. R. Lasker Library, EWU Circulation Section	Non-fiction	621.392 PAD 2004 (Browse shelf(Opens below))	C-3	Available	17509
Text	Dr. S. R. Lasker Library, EWU Circulation Section	Non-fiction	621.392 PAD 2004 (Browse shelf(Opens below))	C-4	Available	20324
Text	Dr. S. R. Lasker Library, EWU Circulation Section	Non-fiction	621.392 PAD 2004 (Browse shelf(Opens below))	C-5	Available	20325

Total holds: 0

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Includes bibliographical references (p. 449-450) and index.

TOC Machine generated contents note: 1. Introduction to VLSI Design --
2. Introduction to Verilog --
3. Language Constructs and Conventions in Verilog --
4. Gate Level Modeling --
1 --
5. Gate Level Modeling --
2 --
6. Modeling at Data Flow Level --
7. Behavioral Modeling --
1 --
8. Behavioral Modeling II --
9. Functions, Tasks, and User-Defined Primitives --
10. Switch Level Modeling --
11. System Tasks, Functions, and Compiler Directives --
12. Queues, Plas, and FSMS --
App. A Keywords and Their Significance --
App. B Truth Tables of Gates an Switches.

ETE

Tahur Ahmed

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