Synthesis and optimization of digital circuits / Giovanni De Micheli
Material type:
Item type | Current library | Collection | Call number | Copy number | Status | Date due | Barcode | Item holds |
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Dr. S. R. Lasker Library, EWU E-book | Non-fiction | 621.3950285 MIS 1994 (Browse shelf(Opens below)) | Not for loan | ||||
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Dr. S. R. Lasker Library, EWU Reserve Section | Non-fiction | 621.395'0285 MIS 1994 (Browse shelf(Opens below)) | C-1 | Not For Loan | 15226 | ||
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Dr. S. R. Lasker Library, EWU Reserve Section | Non-fiction | 621.395'0285 MIS 1994 (Browse shelf(Opens below)) | C-2 | Not For Loan | 15227 | ||
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Dr. S. R. Lasker Library, EWU Circulation Section | Non-fiction | 621.395'0285 MIS 1994 (Browse shelf(Opens below)) | C-3 | Available | 15228 | ||
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Dr. S. R. Lasker Library, EWU Circulation Section | Non-fiction | 621.395'0285 MIS 1994 (Browse shelf(Opens below)) | C-4 | Available | 15229 | ||
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Dr. S. R. Lasker Library, EWU Circulation Section | Non-fiction | 621.395'0285 MIS 1994 (Browse shelf(Opens below)) | C-5 | Available | 15230 |
Chapter 1: Introduction --
Chapter 2: Background --
Chapter 3: Hardware modeling --
Chapter 4: Architectural synthesis --
Chapter 5: Scheduling algorithms --
Chapter 6: Resource sharing and binding --
Chapter 7: Two-level combinational logic optimization --
Chapter 8: Multiple-level combinational logic optimization --
Chapter 9: Sequential logic optimization --
Chapter 10: Cell-library binding --
Chapter 11: State-of-the-art and future trends. TOC
EEE
Shaharima Parvin
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